During the fabrication of such integrated circuits as memory devices, it is conventional to test the integrated circuits at several stages during the fabrication process. For example, the integrated circuits are normally connected to a tester with a probe card when the integrated circuits are still in wafer form. In a final test occurring after the integrated circuits have been diced from the wafer and packaged, the integrated circuits are placed into sockets on a load board. The load board is then placed on a test head, typically by a robotic handler. The test head makes electrical contact with conductors on the load board, and these conductors are connected to the integrated circuits. The test head is connected through a cable to a high-speed tester so that the tester can apply signals to and receive signals from the integrated circuits.
While the above-described testing environment works well in many applications, it is not without its limitations and disadvantages. For example, it is very difficult to test various timing characteristics of the integrated circuits, particularly at the high operating speeds for which such integrated circuits are designed. This difficulty results primarily from the propagation delays in transferring signals through the cable between the tester to the test head. The cables that are typically used in such testing environments are often fairly long, thus making the propagation delays of signals coupled to and from the integrated circuits correspondingly long and often difficult to predict.
With reference to FIG. 1, a conventional tester 2 is coupled to a load board 4 containing several integrated circuits, which, in this example, are dynamic random access memory (“DRAM”) devices 6. The load board 4 is connected to the tester 2 through sets of signal lines, which are represented in FIG. 1 as buses 7. A first set of lines couples respective address (“A”) signals and bank address (“BA”) signals from the tester 2 to the load board 4, and a second set of signal lines couples respective command (“C”) signals from the tester 2 to the load board 4. These command signals may be, for example, a row address select (“RAS”) signal, a column address select (“CAS”) signal, a write enable (“WE”) signal, a reset (“R”) signal, a chip select (“CS”) signal, an on-die termination (“ODT”) signal, and a clock enable (“CKE”) signal. A third set of signal lines couples respective clock (“CLK”) and complementary clock (“CLK*”) signals from the tester 2 to the load board 4. A fourth set of signal lines couples respective data (“DQ”) signals from the tester 2 to the load board 4. Finally, a fifth set of signal lines couples a data strobe (“DQS”) signal and a complementary data strobe (“DQS*”) signal from the tester 2 to the load board 4.
Techniques have been developed to allow the tester 2 to deal with the propagation delays in transferring signals from the tester 2 to the load board 4. For example, in many testers, such as the tester 2 shown in FIG. 1, the tester 2 can vary the timing at which each set of signals are applied to the load board 4. Thus, for example, the timing at which the address A and bank address BA signals are applied to the load board 4 can be adjusted independently of the timing at which the DQ signals are applied to the load board 4. In some cases, the tester 2 can vary the timing at which each signal is applied to the load board 4 on a signal-by-signal basis so that, for example, the timing at which individual DQ signals are applied to the load board 4 can be adjusted independently of each other.
While these and other techniques have been developed to allow the tester 2 to deal with the propagation delays in transferring signals from the tester 2 to the load board 4, these techniques result in testers that are highly complex and often very expensive. A large number of testers are normally required for a high capacity semiconductor fabrication plant, thus greatly increasing the cost of the plant and the expense of testing the integrated circuits.
Another problem with conventional testers, such as the tester 2 shown in FIG. 1, results from a limited range of adjustment at which they can adjust the timing of signals applied to the load board 4. The problem is exemplified by the block diagram of a portion of the tester 2 shown in FIG. 2 and the accompanying timing diagram shown in FIG. 3. With reference to FIG. 2, the tester 2 (FIG. 1) typically includes a signal generator 8 that generate signals, such as a data (“D”) signal, which may have a fixed timing in relation to the other signals generated by the tester 2, e.g., address signals, command signals, etc. The D signal is applied to a latch 9 and is stored in the latch 9 responsive to a core clock (“CCLK”) signal. The stored D signal is clocked out of the latch to provide the DQ signal responsive to a transmit clock (“TCLK”) signal. The tester 2 is able to vary the timing of the TCLK signal to adjust the timing at which the DQ signal is applied to the load board 4.
The relationship between the D, DQ, CCLK and TCLK signals is shown in FIG. 3. A bit Dn of the D signal is clocked into the latch 9 by the rising edge of the CCLK signal at time t0. At time t1, the stored D signal is clocked out of the latch 9 by the rising edge of the TCLK signal to generate bit DQn of the DQ signal. To apply the DQn signal to the load board at an earlier time, the timing of the TCLK signal is reduced to the signal TCLK-EARLY, which is also shown in FIG. 3. However, the TCLK-EARLY signal clocking the D signal out of the latch 9 must follow the time t0 when the CCLK signal clocks the D signal into the latch 9 by a minimum set-up time SU. Similarly, to apply the DQn signal to the load board at a later time, the timing of the TCLK signal is increased to the signal TCLK-LATE, which is also shown in FIG. 3. However, the D signal clocked into the latch 9 by the CCLK signal at time t0 must be held in the latch for a minimum HOLD time until the next D signal is clocked into the latch 9 by the next CCLK rising edge. As a result, the TCLK-LATE signal clocking the D signal out of the latch 9 can occur no later than the HOLD time after the CCLK has clocked the D signal into the latch 9. The rising edge of the TCLK signal must therefore occur after the TCLK-EARLY signal and before the TCLK-LATE signal. As a result, the range of timing adjustment of the TCLK signal is limited, thereby limiting the timing at which the DQ signal can be applied to the load board 4 (FIG. 1). For this reason, the tester 2 may be unable to compensate for large variations in the times at which the tester 2 applies signals to the load board 4.
There is therefore a need for a testing system and method that can allow the timing of signals applied to an integrated circuit load board to be adjusted over a relatively wide range, thereby allowing the testing system and method to compensate for large variations in propagation times of signals applied to the load board.